Most “inrush limiter circuits” fail because they are operating in linear mode during inrush. It’s a design limitation on almost every one.
Imagine a FET is a resistor with a variable resistance. When it’s “off” the resistance is [nearly] infinity and when it’s “on” the resistance is [nearly] zero. That’s all fine and dandy until you add capacitors to the load, like the filter capacitors on VESC and other ESCs. Right when it turns on, it’s effectively a momentary short circuit with [not really…] infinite current because the capacitors are empty. So what the antisparks do is they limit inrush current by turning on not from zero to full blast, but gradually over several milliseconds they ramp from [nearly] infinity to [nearly] zero ohms. It’s this period during the ramp that is the problem, the FET itself is taking almost the entire load due to Ohm’s law because the capacitors have effectively zero resistance to inrush. It’s said to be operating in “linear” or analog mode at this point, as opposed to “digital” mode where everything is either on or off with no in-between. This is extremely stressful to the junctions inside the FET and technically exceeding the design limitations for a very brief period of time. Each time it’s powered-on, it’s taking a tiny bit of damage.
The way to ameliorate this is much the same way a loopkey works – you have a “precharge” circuit where the nonzero inrush-limiting resistance is provided by an actual discrete resistor instead of the FET junction itself. So you have one FET with a heatsinked power resistor in series, that is separate from the one or more FETs on the main power switch.
So in order of operation, you’d have a single FET turn fully on [nearly] instantaneously (digitally) with a resistor in series to charge the filter capacitors, then once the output voltage approached the supply voltage (meaning the capacitors are nearing full charge) then the main FET(s) turn on [nearly] instantaneously (digitally) to supply high-current power to the system. This is never operating in “linear” mode but is “fully digital” and will not suffer the incessant failures that plague the inrush-limiting Vedder design. The power limiting and heating is moved to a discrete resistor instead of burning off the energy inside the FET junction itself, which stays cool during inrush.